Digital Physical Implementation Engineer (m/f)

The division is responsible for design and development of high performance data converters and high speed IOs for FSEUs Communications Business Unit. Our most recent development is a world beating first CMOS 56Gs/s 8 bit ADC for 100G Ethernet and OTU-4 transport systems using coherent receivers:
http://www.fujitsu.com/emea/services/microelectronics/dataconverters/chais/

Working for FSEUs Mixed Signal Division is the opportunity to:

• be part of a highly dedicated team responsible for the development of a diverse range of leading edge products
• stimulate your mind in a challenging design environment
• have access to cutting edge submicron CMOS process technologies (now developing Mixed Signal macros at 65nm and 40nm)

 Responsibilities/Tasks:

• Digital Physical Implementation and Verification including Place and Route, test and clock tree insertion, power analysis/routing etc.
• Assistance with RTL coding, synthesis, formal verification, STA and Test pattern generation
• Interfacing with designers/customers for smooth handover and completion/signoff of digital HLBs and IC layouts.

 Further Requirements:

• Qualified to at least degree level in Electronics or related disciplines
• Minimum of 2 years experience in Digital IC Physical Implementation
• Experience with tools for digital chip implementation (Cadence SOC Encounter, Synopsys Design Compiler)
• Experience in design/simulation of digital circuits and hardware description languages (VHDL / Verilog)
• Good communication and interpersonal skills